From: Maher Sanalla <msanalla@nvidia.com>
Subject: [PATCH] BACKPORT: include/linux/mlx5/driver.h

Change-Id: Idcc3f0c83f3d8c856b411f26e8d4c3a7b9793253
---
 include/linux/mlx5/driver.h | 31 +++++++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -33,6 +33,8 @@
 #ifndef MLX5_DRIVER_H
 #define MLX5_DRIVER_H
 
+#include "../../../compat/config.h"
+
 #include <linux/kernel.h>
 #include <linux/completion.h>
 #include <linux/pci.h>
@@ -56,6 +58,9 @@
 #include <linux/timecounter.h>
 #include <linux/ptp_clock_kernel.h>
 #include <net/devlink.h>
+#include <linux/net_tstamp.h>
+#include <linux/llist.h>
+
 
 #define MLX5_ADEV_NAME "mlx5_core"
 
@@ -457,9 +462,11 @@ struct mlx5_core_health {
 	unsigned long			flags;
 	struct mlx5_fw_crdump		*crdump;
 	struct work_struct		fatal_report_work;
+#ifdef HAVE_DEVLINK_HEALTH_REPORT_SUPPORT
 	struct work_struct		report_work;
 	struct devlink_health_reporter *fw_reporter;
 	struct devlink_health_reporter *fw_fatal_reporter;
+#endif /* HAVE_DEVLINK_HEALTH_REPORT_SUPPORT */
 	struct delayed_work		update_fw_log_ts_work;
 	/* failed recoveries in sequence*/
 	u32 failed_in_seq;
@@ -529,6 +536,7 @@ struct mlx5_core_sriov {
 	struct kobject		*groups_config;
 	struct kobject		node_guid_kobj;
 	struct mlx5_sriov_vf	*vfs;
+	bool			probe_vf;
 };
 
 struct mlx5_fc_pool {
@@ -622,6 +630,12 @@ enum {
 	 * creation/deletion on drivers rescan. Unset during device attach.
 	 */
 	MLX5_PRIV_FLAGS_DETACH = 1 << 2,
+#ifdef HAVE_DEVL_PORT_REGISTER //forward port
+	/* Distinguish between mlx5e_probe/remove called by module init/cleanup
+	 * and called by other flows which can already hold devlink lock
+	 */
+	MLX5_PRIV_FLAGS_MLX5E_LOCKED_FLOW = 1 << 3,
+#endif
 };
 
 struct mlx5_adev {
@@ -661,6 +675,9 @@ struct mlx5_priv {
 	/* IRQ table valid only for real pci devices PF or VF */
 	struct mlx5_irq_table   *irq_table;
 	struct mlx5_eq_table	*eq_table;
+#ifndef HAVE_PCI_IRQ_API
+	struct msix_entry       *msix_arr;
+#endif
 
 	/* pages stuff */
 	struct mlx5_nb          pg_nb;
@@ -871,9 +888,11 @@ struct mlx5_clock {
 	struct mlx5_nb             pps_nb;
 	seqlock_t                  lock;
 	struct hwtstamp_config     hwtstamp_config;
+#if (defined (CONFIG_PTP_1588_CLOCK) || defined(CONFIG_PTP_1588_CLOCK_MODULE))
 	struct ptp_clock          *ptp;
 	struct ptp_clock_info      ptp_info;
 	struct mlx5_pps            pps_info;
+#endif
 	struct mlx5_timer          timer;
 };
 
@@ -965,7 +984,9 @@ struct mlx5_core_dev {
 	enum mlx5_device_state	state;
 	/* sync interface state */
 	struct mutex		intf_state_mutex;
+#ifdef HAVE_LOCKDEP_UNREGISTER_KEY
 	struct lock_class_key	lock_key;
+#endif
 	unsigned long		intf_state;
 	struct mlx5_priv	priv;
 	struct mlx5_profile	profile;
@@ -1047,8 +1068,13 @@ struct mlx5_cmd_work_ent {
 	int			page_queue;
 	u8			status;
 	u8			token;
+#ifdef HAVE_KTIME_GET_NS
 	u64			ts1;
 	u64			ts2;
+#else
+	struct timespec		ts1;
+	struct timespec		ts2;
+#endif
 	u16			op;
 	bool			polling;
 	/* Track the max comp handlers */
@@ -1183,7 +1209,7 @@ void mlx5_cmd_allowed_opcode(struct mlx5
 struct mlx5_async_ctx {
 	struct mlx5_core_dev *dev;
 	atomic_t num_inflight;
-	struct wait_queue_head wait;
+	wait_queue_head_t wait;
 };
 
 struct mlx5_async_work;
@@ -1504,9 +1530,10 @@ bool mlx5_is_roce_on(struct mlx5_core_de
 
 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
 {
+#if defined(HAVE_DEVLINK_PARAM) && defined(HAVE_DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE)
 	if (MLX5_CAP_GEN(dev, roce_rw_supported))
 		return MLX5_CAP_GEN(dev, roce);
-
+#endif
 	/* If RoCE cap is read-only in FW, get RoCE state from devlink
 	 * in order to support RoCE enable/disable feature
 	 */
