From: Valentine Fatiev <valentinef@nvidia.com>
Subject: [PATCH] BACKPORT: drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c

Change-Id: I5cbc252c9fbc1a4365c36cdc86ca31cb5722493f
---
 .../ethernet/mellanox/mlx5/core/en_dcbnl.c    | 63 +++++++++++++++++--
 1 file changed, 57 insertions(+), 6 deletions(-)

--- a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c
@@ -61,6 +61,7 @@ enum {
 				   MLX5_CAP_QCAM_REG(mdev, qpts) && \
 				   MLX5_CAP_QCAM_REG(mdev, qpdpm))
 
+#ifdef CONFIG_MLX5_CORE_EN_DCB
 static int mlx5e_set_trust_state(struct mlx5e_priv *priv, u8 trust_state);
 static int mlx5e_set_dscp2prio(struct mlx5e_priv *priv, u8 dscp, u8 prio);
 
@@ -901,6 +902,7 @@ static void mlx5e_dcbnl_setpfcstate(stru
 	cee_cfg->pfc_enable = state;
 }
 
+#ifdef HAVE_DCBNL_GETBUFFER
 static int mlx5e_dcbnl_getbuffer(struct net_device *dev,
 				 struct dcbnl_buffer *dcb_buffer)
 {
@@ -984,8 +986,13 @@ static int mlx5e_dcbnl_setbuffer(struct
 					      buffer_size, prio2buffer);
 	return err;
 }
+#endif
 
+#ifdef CONFIG_COMPAT_IS_DCBNL_OPS_CONST
 static const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = {
+#else
+struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = {
+#endif
 	.ieee_getets	= mlx5e_dcbnl_ieee_getets,
 	.ieee_setets	= mlx5e_dcbnl_ieee_setets,
 	.ieee_getmaxrate = mlx5e_dcbnl_ieee_getmaxrate,
@@ -996,8 +1003,10 @@ static const struct dcbnl_rtnl_ops mlx5e
 	.ieee_delapp    = mlx5e_dcbnl_ieee_delapp,
 	.getdcbx	= mlx5e_dcbnl_getdcbx,
 	.setdcbx	= mlx5e_dcbnl_setdcbx,
+#ifdef HAVE_DCBNL_GETBUFFER
 	.dcbnl_getbuffer = mlx5e_dcbnl_getbuffer,
 	.dcbnl_setbuffer = mlx5e_dcbnl_setbuffer,
+#endif
 
 /* CEE interfaces */
 	.setall         = mlx5e_dcbnl_setall,
@@ -1149,18 +1158,29 @@ static int mlx5e_update_trust_state_hw(s
 
 static int mlx5e_set_trust_state(struct mlx5e_priv *priv, u8 trust_state)
 {
+#if defined(HAVE_NDO_SETUP_TC_TAKES_TC_SETUP_TYPE) || defined(HAVE_NDO_SETUP_TC_RH_EXTENDED)
+#ifdef HAVE_TC_MQPRIO_QOPT_OFFLOAD
 	struct tc_mqprio_qopt_offload mqprio = {.qopt.num_tc = MLX5E_MAX_NUM_TC};
+#else
+	struct tc_mqprio_qopt mqprio = {.num_tc = MLX5E_MAX_NUM_TC};
+#endif
+#endif
+
 	struct mlx5e_params new_params;
 	bool reset = true;
 	int err;
 
 	mutex_lock(&priv->state_lock);
+#if defined(HAVE_NDO_SETUP_TC_TAKES_TC_SETUP_TYPE) || defined(HAVE_NDO_SETUP_TC_RH_EXTENDED)
+#ifdef HAVE_TC_MQPRIO_QOPT_OFFLOAD
 	mqprio.mode = priv->channels.params.mqprio.mode;
 	if (mqprio.mode != TC_MQPRIO_MODE_DCB) {
 		netdev_err(priv->netdev, "Can't change trust state while in channel mode.\n");
 		err = -EINVAL;
 		goto unlock;
 	}
+#endif
+#endif
 
 	new_params = priv->channels.params;
 	mlx5e_params_calc_trust_tx_min_inline_mode(priv->mdev, &new_params,
@@ -1173,22 +1193,41 @@ static int mlx5e_set_trust_state(struct
 	err = mlx5e_safe_switch_params(priv, &new_params,
 				       mlx5e_update_trust_state_hw,
 				       &trust_state, reset);
+#if defined(HAVE_NDO_SETUP_TC_TAKES_TC_SETUP_TYPE) || defined(HAVE_NDO_SETUP_TC_RH_EXTENDED)
+#ifdef HAVE_TC_MQPRIO_QOPT_OFFLOAD
 unlock:
+#endif
+#endif
 	mutex_unlock(&priv->state_lock);
 	if (err)
 		return err;
 
 	/* In DSCP trust state, we need 8 send queues per channel */
-	if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP) {
-		mutex_lock(&priv->state_lock);
-		mlx5e_setup_tc_mqprio(priv, &mqprio);
-		mutex_unlock(&priv->state_lock);
-	} else if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_PCP) {
+	if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP)
+#if defined(HAVE_NDO_SETUP_TC_TAKES_TC_SETUP_TYPE) || defined(HAVE_NDO_SETUP_TC_RH_EXTENDED)
+       {
+	       mutex_lock(&priv->state_lock);
+	       mlx5e_setup_tc_mqprio(priv, &mqprio);
+	       mutex_unlock(&priv->state_lock);
+       }
+#else
+	mlx5e_setup_tc(priv->netdev, MLX5E_MAX_NUM_TC);
+#endif
+	else if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_PCP)
+#if defined(HAVE_NDO_SETUP_TC_TAKES_TC_SETUP_TYPE) || defined(HAVE_NDO_SETUP_TC_RH_EXTENDED)
+	{
 		mutex_lock(&priv->state_lock);
+#ifdef HAVE_TC_MQPRIO_QOPT_OFFLOAD
 		mqprio.qopt.num_tc = priv->pcp_tc_num;
+#else
+		mqprio.num_tc = priv->pcp_tc_num;
+#endif
 		mlx5e_setup_tc_mqprio(priv, &mqprio);
 		mutex_unlock(&priv->state_lock);
 	}
+#else
+	mlx5e_setup_tc(priv->netdev, priv->pcp_tc_num);
+#endif
 
 	return 0;
 }
@@ -1210,12 +1249,19 @@ static int mlx5e_trust_initialize(struct
 	struct mlx5_core_dev *mdev = priv->mdev;
 	int err;
 	u8 trust_state;
+
+#if defined(HAVE_NDO_SETUP_TC_TAKES_TC_SETUP_TYPE) || defined(HAVE_NDO_SETUP_TC_RH_EXTENDED)
+#ifdef HAVE_TC_MQPRIO_QOPT_OFFLOAD
 	struct tc_mqprio_qopt_offload mqprio = {.qopt.num_tc = MLX5E_MAX_NUM_TC};
+#else
+	struct tc_mqprio_qopt mqprio = {.num_tc = MLX5E_MAX_NUM_TC};
+#endif
+#endif
 	const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
 
 	if (!MLX5_DSCP_SUPPORTED(mdev)) {
 		WRITE_ONCE(priv->dcbx_dp.trust_state, MLX5_QPTS_TRUST_PCP);
- 		return 0;
+		return 0;
 	}
 
 	err = mlx5_query_trust_state(priv->mdev, &trust_state);
@@ -1238,7 +1284,11 @@ static int mlx5e_trust_initialize(struct
 	if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP) {
 		if (take_rtnl)
 			rtnl_lock();
+#if defined(HAVE_NDO_SETUP_TC_TAKES_TC_SETUP_TYPE) || defined(HAVE_NDO_SETUP_TC_RH_EXTENDED)
 		mlx5e_setup_tc_mqprio(priv, &mqprio);
+#else
+		mlx5e_setup_tc(priv->netdev, MLX5E_MAX_NUM_TC);
+#endif
 		if (take_rtnl)
 			rtnl_unlock();
 	}
@@ -1291,3 +1341,4 @@ void mlx5e_dcbnl_initialize(struct mlx5e
 
 	mlx5e_ets_init(priv);
 }
+#endif
